1. Field of the Invention
The present invention generally relates to memory circuits. More particularly, this invention relates to a two-bit memory cell array addressing circuits with three to six series bit line selecting function.
2. Description of the Prior Art
A two-bit data stored memory cell is a special Metal Oxide Semiconductor (MOS) field effect transistor comprised of two storage areas under a gate. The MOS memory cell includes a source, a drain, and a gate. Various voltages are applied to the source, the drain and the gate to read the stored data in the storage, to program the cell, and to erase the cell. The drain and the source which consist of diffusion area are usually called as bit lines (BL's) because the stored bit data appears to the bit lines as a voltage or a current in read operation.
One of two-bit data stored memory cells is described in U.S. Pat. No. 6,248,633 (Ogura et al) directed toward a twin MONOS cell structure. The twin MONOS cell of which a schematic is shown in FIG. 1 includes two bit lines BL_l and BL_r and two nitride storage sites M_l and M_r under ultra short control gates CG_l and CG_r beside a word line gate WL. Another two-bit data stored memory cell is described in U.S. Pat. No. 6,011,725 (Eitan) directed toward a method of detecting and writing the content into one of two nitride storage site of a cell known well as NROM.
A simplified example of voltage conditions for the read operation in the twin MONOS cell is shown in FIG. 1. The bit line BL_r is connected to the ground (0V). A precharge voltage (1.8V in this example) is applied to the bit line BL_l. This makes the bit line BL_l floating. A word line voltage (1.8V), a select CG voltage (1.8V) and an override CG voltage (3.3V) are applied to WL, CG_r and CG_l, respectively, to turn on the memory cell transistor. Under these conditions, cell current flows from the bit line BL_l to the bit line BL_r through the memory cell transistor with magnitude of the current depending on charge stored in the storage site of right side M_r, and then the current affects the voltage of the bit line BL_l at a time. The bit line voltage is sensed and the bit data stored in the right side storage M_r is provided.
A prior art of simplified example voltage conditions for the program operation in the twin MONOS cell is shown in FIG. 2. The bit line BL_r is connected to a high voltage (5V). A program voltage (0V) or a program-inhibit voltage (1.8V) is applied to the other bit line BL_l. A word line voltage (1V), a select CG voltage (5V) and a override CG voltage (3.3V) are applied to WL, CG_r and CG_l, respectively, to turn on the memory cell transistor. When the bit line voltage of left side BL_l is the program voltage (0V), cell current flows, electrons accumulate in the right storage site M_r, and then the storage site is programmed. When the bit line voltage of left side BL_l is the program-inhibit voltage (1.8V), no cell current flows and the right storage site M_r maintains its erased condition.
In each operation, the voltage of the bit line in left side depends on the stored data in the right storage site or programmed data to the right storage site. Consequently, the bit line is hereinafter referred to as BL_data. In contrast, however, the voltage of the bit line in the right side is not changed by the sensed or programmed data. Because the bit line is coupled to another bit line of the adjacent memory cell in a memory array structure, the bit line is hereinafter referred to as BL_common. For example, in a read operation, 0V is applied to BL_common, and a voltage of BL_data is sensed. In program operation, voltages of BL_data and BL_common are 0V (or 1.8V) and 5V, respectively.
FIGS. 3(a) and (b) are memory array cross-sections of twin MONOS cells, which are disclosed in U.S. Pat. No. 6,248,633 (Ogura et al) and U.S. patent application Ser. No. 10/190634 (Ogura et al) “Twin MONOS array metal bit organization and single cell operation”, respectively. When the memory is arrayed, the control gates above M_r and M_l of adjacent memory cells may be connected together in a stitch area such that the two nodes are schematically and functionally equivalent.
Two twin MONOS cells located in adjacent placement are accessed at the same time to select three series bit lines. For example, in FIG. 3a, a nitride storage site in right side of memory cell 54 and a nitride storage site in left side of memory cell 55 are read or programmed as follows. Bit line 64 which is shared with the selected memory cells 54 and 55 is selected as BL_common. Bit lines 63 and 65 which are bit lines in the opposite side of BL_common in the selected memory cells 54 and 55 are selected as BL_data in left and right sides, respectively. Bit line voltages for BL_common and BL_data are applied to the selected bit lines. Word line voltage, select CG voltage and override CG voltage are applied to word line 30, control gate 44 and control gate 43 and 45 in case of FIG. 3(a). In the case of FIG. 4(b), the selected CG voltage is higher, and the BL_data voltage is selected based on the input data.
Otherwise, for the memory array of FIG. 3(b), which denotes sample voltages during programming, memory cell selection is similar to that shown in FIG. 3(a).
There is an additional concern about the other BL's outside of BL_data and BL_common. These other BL's will be divided into two categories, BL_neighbor and BL_others. The BL_neighbor refers to the BL that is next to a BL_data, and that is not a BL_common. In order to prevent leakage, BL_neighbor's may be fixed to some intermediate voltage (1.8V for example), so that the voltage of BL_data is not compromised, especially during program or read. Note that this constraint to BL_neighbor is not required when BL_data is connected to the edge bit line of a memory array.
Some of sensing schemes require a reference voltage which is used to compare the voltage of BL_data. To process the comparison accurately, same noises in BL_data caused by word line coupling and CG line coupling should be provided to the node of the reference voltage. One of the ways to provide the noises to the reference node is to use an unused bit line as the reference node, and thus the neighboring bit line of left or right BL_neighbor can be used for the reference node. In case of no BL_neighbor, i.e. the memory array of FIG. 3(a), the neighboring bit line of left or right BL_data would be used. Consequently the bit line for the reference node is hereinafter referred to as BL_refer.
As described above, a pair of three to six series bit lines is selected, of which the number is determined by memory array structure and sensing scheme. In the case of a pair of three series bit lines selected, the order of the bit lines is left BL_data, BL_common and right BL_data from left to right. In the case of a pair of four series bit lines selected, the order of the bit lines is left BL_data, BL_common, right BL_data and BL_refer, or BL_refer, left BL_data, BL_common, and right BL_data from left to right. In the case of a pair of five series bit lines selected, the order of the bit lines is left BL_neighbor, left BL_data, BL_common, right BL_data and right BL_neighbor from left to right. In the case of a pair of six series bit lines selected, the order of the bit line's is left BL_neighbor, left BL_data, BL_common, right BL_data, right BL_neighbor and BL_refer, or BL_refer, left BL_neighbor, left BL_data, BL_common, right BL_data and right BL_neighbor from left to right. Note that these bit line combinations may be used beneficially in other memory arrays such as an array of NROM cells.
A bit line decoder provides connection of the bit line pair to circuit elements which apply or sense a voltage and provides disconnection of unselected bit lines of a plural of bit lines in a memory array to the circuit elements. A purpose of the present invention is to present a bit line decoder to support selection of a pair of three to six bit lines.
FIG. 4a shows a prior art of a bit line decoder 199 to connect a pair of three bit lines to circuit elements for BL_common and BL_data. The bit line decoder 199 includes two group circuits 299 and 399 of which each selects a pair of three series bit lines (BL_common and two BL_data) from 16 bit lines BLn[0]-BLn[15], applies a voltage to BL_common of the pair and sense a voltage of BL_data to output logic level signal of the sensing result or provide a voltage to BL_data based on input logic level signal, where n identifies the group number. The group circuit 299 in the 0th group includes bit lines BL0[0-15], pass transistors 240-255, 270-273, 280-283 and 290-293, intermediate nodes 220-223, a voltage node 230 for BL_common, and sense/driver circuit elements 235 and 236. The bit lines BL0[0]-BL0[15] in the memory array are connected to the first stage pass transistors 240-255, separately. A pass transistor may consist of an n-channel MOS transistor, or a p-channel MOS transistor or complementary MOS (CMOS) high voltage transistor pair, and the pass transistor controls connection of a bit line to an intermediate node by a control gate. Control gates of the pass transistors 240-255 are connected to control signals A[0]-A[15] separately, and every four pass transistors are connected together to one of four intermediate nodes 220-223. The intermediate nodes are connected to the last stage pass transistors 270-273, 280--83 and 290-293 controlled by control signals S[0]-S[3], then the pass transistors 270-273 are connected to a node 230 to apply a voltage for BL_common from a common voltage node 190 and the pass transistors 280-283 and 290-293 are connected to nodes 231 and 232, respectively, which are terminals of left and right sense/driver circuit elements 235 and 236 (D0L and D0R), respectively. In read operation, the left and right sense/driver circuit elements 235 and 236 sense the voltage of the terminals 231 and 232, respectively, which are coupled to left and right BL_data, respectively, through the first and last stage pass transistors, and output logic level signals of the sensing results to nodes 233 and 234, respectively. In program operation, the sense/driver circuit elements 235 and 236 input logic level signals of programming data from the nodes 233 and 234, respectively, and provide voltages corresponding to the input signals to the terminals 231 and 232, respectively, which are coupled to left and right BL_data, respectively, through the first and last stage pass transistors. The same group circuit is repeated to the 1st group circuit 399 and more group circuits can be repeated.
The bit line decoder 199 further includes bit lines BLE_L, BLE_R, pass transistors 440, 455, 483 and 490, intermediate nodes 420 and 423, and sense/driver circuit elements 435 and 436. The bit lines BLE_L and BLE_R are connected to the first stage pass transistors 455 and 440 separately. Control gates of the pass transistors 455 and 440 are connected to control signals A[15] and A[0], respectively, and connected to intermediate nodes 423 and 420, respectively. The intermediate nodes 423 and 420 are connected to the last stage pass transistors 483 and 490, respectively, controlled by control signals S[0] and S[3], respectively, and the pass transistors 483 and 490 are connected to nodes 431 and 432, respectively, which are terminals of left and right sense/driver circuit elements 435 and 436 (DEL and DER), respectively, including nodes 433 and 434 for input/output logic level signal.
The table in FIG. 4b shows the operation of control signals A[0]-A[15] and S[0]-S[3]. Regarding of the control signals, actual “open” and “close” voltages of the control signal are dependent on the kind of a pass transistor. When an n-channel MOS transistor is used as the pass transistor, the control signal is active high, and high (˜6V) and low (0V) voltages may be applied for “open” and “close” voltages, respectively. When a p-channel MOS transistor is used as the pass transistor, the control signal is active low, and low (˜1V) and high (5V) voltages may be applied for “open” and “dose” voltages, respectively. When CMOS transistor set is used as the pass transistor, the control signal consists of two lines. And one of the lines is active high and the other is active low.
Regardless of the type of pass transistor, the voltage range of a control signal is wider than a logic voltage range for a digital logic circuit. (The logic voltage range is between 0V and 1.8V, although it depends on process technology.) Thus, a transistor for high voltage tolerance with thick gate oxide may be used in a driver of the control signal instead of using a transistor for logics. And a large driver consisting of the high voltage transistor is needed to drive the control signal of which capacitance is large because of a lot of connection of pass transistors gates. Since a high voltage transistor requires a large layout area due to process reason, the layout of the driver for the control signal becomes large. Moreover, a voltage level shifter circuit which changes the voltage of input high (or low) level to a higher (or lower) voltage and which uses a large layout area is required to exchange output of logic circuits to control signal voltage level. Then total layout area for control signal drivers becomes large because of the large number of control signals.
U.S. Pat. No. 6,248,633 (Ogura, et al.) describes a process for making and programming and operating a dual-bit multi-level ballistic MONOS memory. A fast low voltage ballistic program, ultra-short channel, high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process.
U.S. Pat. No. 6,011,725 (Eitan) describes a two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping. The non-volatile electrically erasable programmable read only memory (EEPROM) is capable of storing two bits of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators.
U.S. Pat. No. 6,181,597 (Nachumovsky) describes a structure and method for implementing an EEPROM array using 2-bit non-volatile memory cells arranged in a plurality of rows and columns. A serial read operation is used in this structure and method.
U.S. Pat. No. 6,081,456 (Dadachev) describes bit line control circuit for a memory array using 2-bit non-volatile memory cells, where each memory cell has a first and a second charge trapping region. There are a set of bit lines extends between the array and the bit line control circuit.